The present invention disclosed herein relates to semiconductor memory devices and more particularly, to nonvolatile semiconductor memory devices storing multi-bit data.
Semiconductor memory devices are generally classified as either volatile or nonvolatile memories. Volatile semiconductor memory devices lose stored data in the absence of supplied power, whereas non-volatile semiconductor memory device retain stored data even when the supply of power is interrupted. Examples of nonvolatile semiconductor memory devices include mask ROMs (MROMs), programmable ROMs (PROMs), erasable and programmable ROMs (EPROMs), electrically erasable and programmable ROMs (EEPROMs), and so on. Among these, the flash-type EEPROM (hereinafter, referred to as ‘flash memory’) is especially suited as a large-capacity auxiliary storage unit since it allow for a high integration density when compared with more conventional EEPROMs.
Flash memories are usually classified as either NOR type or NAND type flash memories in accordance with the manner in which the memory cells thereof are connected to bit lines. The NOR flash memory is configured such that one bit line is coupled to two or more cell transistors in parallel. Further, in the NOR flash memory, data is stored by channel hot electron injection and erased by Folwer-Nordheim (F-N) tunneling effect. In contrast the NAND flash memory is configured such that one bit line is coupled to two or more cell transistors in series. Also, in the NAND flash memory, data is stored and erased by means of the F-N tunneling effect. In general, the NOR flash memory is capable of relatively high frequency operations, but is difficult to implement at high densities due in part to its large power consumption. However, in an effort to increase cell density, NOR flash memories are being develop with multi-level cell (MLC) capabilities.
FIG. 1 is a diagram showing threshold voltage distribution profiles associated with data of flash memory cells in the MLC scheme. In contrast to a single-level cell scheme where each cell is programmed to one of two voltage distributions to store one-bit date, the MLC scheme of FIG. 1 is characterized by each cell being programmed into one of four different threshold voltage distributions to store two-bit data.
As an example, data values stored in the unit cell may be arranged in the order of ‘11’, ‘10’, ‘01’, and ‘00’ in the order of the lowest to highest threshold voltages. The lowest threshold voltage data ‘11’ corresponds to an erased state, from which a programming operation begins. An MLC flash memory device storing multi-bit data in a single memory cell is disclosed, for example, in U.S. Pat. No. 6,101,125 entitled ‘ELECTRICAL PROGRAMMING MEMORY AND METHOD OF PROGRAMMING’.
FIG. 2 is a flowchart illustrating a conventional MLC programming method operable in a NOR flash memory device, which is disclosed in the afore-mentioned U.S. Pat. No. 6,101,125.
Referring to FIG. 2, the MLC programming operation of the NOR flash memory device begins from the erased state ‘11’. The procedure of MLC programming is carried out in the sequence of programming data ‘10’ (S100), program-verifying data ‘10’ (S110), programming data ‘01’ (S120), program-verifying data ‘01’ (S130), programming data ‘00’ (S140), and program-verifying data ‘00’ (S150), in this order. The distribution profiles of threshold voltages must be densely controlled to be confined in their windows in correspondence with the four data states. For this reason, there has been proposed a programming routine using an incremental step pulse programming (ISPP) scheme. According to the ISPP scheme, a threshold voltage increases by an incremental portion of a program loop or voltage. In this manner, the distribution profiles of threshold voltages can be densely regulated by reducing the incremental portion of program voltage. This makes it possible to assure sufficient margins between the data states.
FIGS. 3 and 4 are waveform diagrams showing examples of variations of word line voltages Vpgm and Vvfy and a bulk voltage VBULK that are applied thereto during the conventional MLC programming operation according to the ISPP scheme.
From FIGS. 2 through 4, it can be seen that the conventional multi-bit programming operation is carried out by alternate execution of programming and program-verifying steps with a stepped-up program voltage. For example, as shown in FIG. 3, after a first program voltage Vpgm10_step1 is applied to conduct a first programming step, a program-verifying step begins with a verifying voltage Vvfy10. Thereafter, a second program voltage Vpgm10_step2 higher than Vpgm_step1) is applied to conduct a second programming step and then another program-verifying step begins with the verifying voltage Vvfy10. In FIGS. 3 and 4, the verifying voltage Vvfy10 is higher than the program voltages Vpgm10_step1 and Vpgm10_step2.
Generally, in the conventional multi-bit programming mode where the program voltages (e.g., Vpgm10_step1, Vpgm10_step2, and so on) alternate with the verifying voltage (e.g., Vvfy10), it is essentially required of recovery and setup periods to rapidly change voltage levels for every generation of the voltages. As a result, such frequent generation of the recovery and setup periods increases a programming time, and can also result in an inadvertent voltage overshoot. These drawbacks may also arise from the bulk voltage, as well as the word line voltages, as shown in FIG. 4.